Layout Design Summary for DCDC Switching Power Supplies
1, deal with the feedback loop (corresponding to the above figure in the R1-R2-R3-IC_FB & GND), the feedback line do not go under the Schottky, do not go under the inductance (L1), do not go under the large capacitors, do not be surrounded by large current loop, if necessary, in the sampling resistor and a 100pF capacitor to increase the stability (but transients will be affected by the slightest);.
2, the feedback line would rather fine than thick, because the wider the line, the more obvious antenna effect, affecting the stability of the loop. Generally use 6-12mils of line.
3, all capacitors as close as possible to the IC.
4, inductance according to the specifications of the indicators of 120-130% of the capacity selection, not too large, too large will affect the efficiency and transient; 5, capacitance according to the specifications of the 120-130% of the capacity selection.
5, capacitors according to the specifications of the 150% capacity selection. If the chip ceramic capacitors, if you use 22uF, with two 10uF parallel connection will be better. If the cost is not sensitive, the capacitor can be larger. Special note: output capacitance, if the use of aluminium electrolytic capacitors, always remember to use high-frequency low-resistance, not just put a low-frequency filter capacitors!
6, as far as possible to reduce the encircling area of the high-current loop. If it is not convenient to narrow, with the copper way into a narrow slit.
7, do not use thermal resistance pads on critical loops, they will introduce excess inductive properties.
8, When using ground layers, make every effort to maintain the integrity of the ground layer below the input switching loop. Any cutting of the ground layer in this area will reduce the effectiveness of the ground layer and increase the impedance of the signal via holes even through the ground layer.
9. The vias can be used to connect the decoupling capacitor and IC ground to the ground layer, which minimises the loop. However, it should be kept in mind that the inductance of the vias ranges from about 0.1 to 0.5nH, depending on the thickness and length of the vias, and they increase the total loop inductance. For low impedance connections, the use of multiple vias is desirable.
In the example above, the additional vias to the ground layer do not help to reduce the length of the C IN loop. However, in the other example, since the top layer has a long path, it is very effective to reduce the loop area through the vias.
It should be noted that using the ground layer as a current return path introduces a large amount of noise into the ground layer, so the local ground layer can be isolated and connected to the main ground through a very low noise point.
