Data Acquisition System for Detection of Transient Optical Radiation Signal
According to the characteristics of strong background and weak target in transient optical radiation detection, this paper designs a data acquisition scheme with FPGA as the core of control and processing. The scheme adopts background and signal double filter channels, two-level program-controlled amplification, which effectively guarantees the quality of signal acquisition; at the same time, it adopts frequency conversion storage for target signals, which greatly reduces the requirements for data storage and transmission, and ensures a more consistent acquisition process. measurement accuracy.
1 System composition and working principle
The data acquisition system can be roughly divided into three parts: the pre-processing module, the sampling storage module, and the FPGA control module. The pre-processing module includes photoelectric conversion devices, active filter banks, and program-controlled amplifier circuits. The block diagram of the entire system is shown in Figure 1. The photoelectric conversion circuit converts the optical signal entering the system into a current signal through a detector, and then converts it into a voltage signal through a transimpedance operational amplifier. The system designs two filtering channels: the background adopts low-pass filtering, and the signal adopts high-pass filtering. In the initial state, the analog switch selects the background channel by default, and the programmable amplifier is set to the background mode. After the background signal is sampled by A/D, it is sent to FPGA for threshold comparison. When a situation greater than the threshold is detected, the FPGA switches the channel of the analog switch, the channel of the high-pass filter is selected, and the operating mode of the program-controlled amplifier is selected as the signal mode. According to the characteristics of the signal being steep at the beginning and slow at the end, the FPGA realizes the collection and storage of data densely and then sparsely through the coordinated control of A/D and FIFO.
2. Hardware Design of Data Acquisition System
2.1 Front stage preprocessing circuit
In the photoelectric detection circuit, the photodetector is directly related to the quality of the system performance. In order to reduce the influence of induced current caused by environmental electromagnetic radiation, the device is suitable for ceramic packaging. In addition, the photosensitive area of the detector should not be too large, otherwise parameters such as dark current, junction capacitance, and rise time will increase, which will affect the detection effect. In the design, the S2387 silicon photodiode of Japan Hamamatsu Company is used. The detector has the characteristics of high sensitivity, fast time response and large dynamic range. The circuit design adopts zero bias mode, no dark current, the diode noise is mainly the thermal noise generated by the shunt resistor, and it has the best precision and linearity. The high and low pass filter adopts active filter, which has fast response speed, good effect of filtering harmonics, and can dynamically compensate reactive power. The program-controlled amplifier is composed of an integrated operational amplifier and an analog switch. The analog switch is controlled by FPGA, and different resistors are connected to the input terminal of the operational amplifier to adjust the gain.
2.2 Sampling storage circuit
Because the dynamic range of the target signal is very large (about 80 dB), it is necessary to select an ADC with a wide dynamic range to realize the acquisition of the signal. Adopting 14 b ADC to sample the signals with a dynamic range whose amplitude varies up to 4 orders of magnitude can meet the requirements of high detection sensitivity required by the system. However, since all A/D conversion devices have precision errors, using high-precision A/D conversion components as low-precision A/D conversion components can reduce precision errors. This design uses 16 bAD976A of ADI Company. AD976A low power consumption 16 b successive approximation A/D converter, the conversion speed is 200 KSPS, can choose internal or external 2.5 V reference power supply. AD976 allows 16 b to output in parallel at one time, and can output in the form of two 8 b. In order to save pins in the design, dual 8 b outputs are adopted.
In order to ensure accurate transmission of data between different clock domains, the data cache uses an asynchronous FIFO. The asynchronous FIFO has the characteristics of high speed and good reliability, and can avoid mis-sampling of data due to phase differences between different clocks. The IDT7204 adopted in the design is a 4 096 × 9 b CMOS dual-port memory cache chip in the IDT72XX series. The internal read and write pointers are read and written on the basis of first-in first-out, and the write clock W and read clock R are provided externally; the full flag () and the empty flag () control data overflow and empty reading, and write when the simulation memory is full It can easily expand any word depth and word length.
