Summary of layout design of DC switching power supply
The layout of DC-DC is very important and will directly affect the stability and EMI effect of the product. The summary experience/rules are as follows:
1. Handle the feedback loop well (corresponding to R1-R2-R3-IC_FB&GND in the above figure), the feedback line should not go under the Schottky, don’t go under the inductor (L1), don’t go under the large capacitor, don’t be surrounded by high current loops , if necessary, the sampling resistor and a 100pF capacitor can be used to increase stability (but the transient will be affected a little);
2. The feedback line should be thin rather than thick, because the wider the line, the more obvious the antenna effect, which will affect the stability of the loop. Generally use 6-12mils wire;
3. All capacitors should be placed as close as possible to the IC;
4. The inductance is selected according to the capacity of 120-130% of the specification index, and it should not be too large, which will affect the efficiency and transient state;
5. The capacitor is selected according to the capacity of 150% of the specification. If you use chip ceramic capacitors, if you use 22uF, it would be better to use two 10uF in parallel. If the cost is not sensitive, the capacitor can be larger. Special reminder: if you use an aluminum electrolytic capacitor for the output capacitor, remember to use a high-frequency and low-resistance capacitor, and don’t just put a low-frequency filter capacitor!
6. Minimize the encircled area of the large current loop as much as possible. If it is inconvenient to shrink, use copper to form a narrow slit.
7. Do not use thermal resistance pads on critical circuits, they will introduce redundant inductive characteristics.
8. When using ground planes, try to maintain the integrity of the ground plane below the input switching loop. Any cutting of the ground plane in this area will reduce the effectiveness of the ground plane, and even signal vias through the ground plane will increase its impedance.
9. Via holes can be used to connect decoupling capacitors and IC ground to the ground plane, which can minimize the loop. But keep in mind that the inductance of vias is about 0.1~0.5nH, which will vary according to the thickness and length of vias, and they can increase the total loop inductance. For low-impedance connections, multiple vias should be used.
In the above example, the additional vias to the ground plane did not help to reduce the length of the C IN loop. But in another example, because the path on the top layer is very long, it is very effective to reduce the loop area through via holes.
10. It should be noted that using the ground layer as the path of current return will introduce a lot of noise into the ground layer. For this reason, the local ground layer can be isolated and connected to the main ground through a low-noise point.
11. When the ground layer is very close to the radiation loop, its shielding effect on the loop will be effectively strengthened. Therefore, when designing a multi-layer PCB, the complete ground plane can be placed on the second layer so that it is directly below the top layer that carries a large current.
12. Unshielded inductors will generate a large amount of magnetic flux leakage, which will enter other loops and filter components. In noise-sensitive applications, semi-shielded or fully shielded inductors should be used, and sensitive circuits and loops should be kept away from the inductor.
