Progress in Linear Power Supply LDO Research
Recently, Professor Mingxin's research group from the Power Integration Technology Laboratory of the School of Integrated Circuit Science and Engineering at the University of Electronic Science and Technology of China published a breakthrough research result on low-power fast transient technology in the field of low dropout linear regulators (LDOs) in the IEEE Solid State Circuit Journal.
This technology can significantly improve the high-speed photography performance of smartphones and drones. It adopts advanced load current recovery and active clamp control architecture, with a static power consumption of only 8.2 μ A. It can simultaneously handle high and low frequency load transient changes, compress the LDO transient quality factor to 41ps, and achieve the fastest high-frequency load jump capability in the high current LDO industry for the first time.
Mobile devices generally adopt a point-to-point power supply architecture consisting of lithium battery cascaded multiple Buck converters and LDOs. Buck is used for high-efficiency voltage reduction, while LDO converts the output ripple voltage of Buck into a stable power supply. The key challenge facing LDO design is that for applications such as Flash Memory with low input voltage and high load current, LDOs typically use N-type power transistors to reduce chip area and optimize transient performance. Due to the unique drive dead zone issue of NMOS-LDO, high-frequency load transients can significantly degrade transient performance; At the same time, the static power consumption of LDO needs to be minimized to prolong battery life, but the pursuit of low power consumption deteriorates the key performance of LDO, such as transient and power suppression ratio.
Based on the above challenges, the research team has designed a static current recovery and near zero driving dead zone LDO control architecture, and proposed a new buffer architecture for transconductance enhanced MOS. While effectively driving the gate capacitance of the power transistor, the static power consumption is completely recovered by the load; The active clamp circuit is used to quickly and accurately clamp the lower limit of the output voltage of the error amplifier when the output voltage is overshoot, reducing the LDO drive dead zone to a near zero state.
With the help of the above technology, LDO was designed to achieve a quality factor of 41ps at a consumption of only 8.2 μ A, while the output voltage fluctuation during high-frequency transients increased by only 40% compared to low-frequency transients. Compared with the international advanced research level, it has significant advantages in high-speed and low-power response.
