What Is the Principle of Power Supply Monitoring?
The reliable operation of a system usually depends on the quality of the power supply. Low power supply voltage can cause failure operations, such as sending failure data to memory or external devices by microcontrollers, FPGAs, or ASICs. Excessive voltage can cause permanent damage to the device. In addition to providing protection during voltage fluctuations, users may also need to identify the source of the fault.
Basic principle:
Use a voltage regulator, a pair of FETs, and several resistors to achieve power shutdown function. The dual line interface and fault register of the voltage regulator should provide fault monitoring capability, and an EPROM (recommended address capacity of 4KB) should be provided to store manufacturing information and maintenance service card information. This voltage regulator monitors three input voltages with voltage thresholds of 4.6, 2.9, and 1.0V, respectively. The circuit shown in the figure provides a configuration where if the 5V power supply voltage is too low, or if the 3.3V power supply voltage is too low or too high, the 3.3V output is turned off.
If the 5V power supply voltage is too low, or the 3.3V power supply voltage is too low or too high, the overvoltage/undervoltage shutdown circuit will shut off the 3.3V output.
The design adopts a metal oxide field-effect transistor (MOSFET) Q1 as the main conducting element or switch. MOSFET is a PMOS device that only requires 2.5V VGS to conduct, so it can function when the power supply voltage drops to 2.5V, and its RDS (on resistance) is also less than 0.1 ohms. The voltage regulator controls the gate of the FET through a FET (Q3) with a maximum VGS of 2.5V. In low voltage situations, MOSFETs and FETs can be replaced with dual MOSFETs, such as Siliconix's Si4913, which has a VGS of 1.8V and an RDS (on resistance) of 24 milliohms at 1.8V voltage.
In this example, the VCC monitoring of the voltage regulator is completed by Intersil's X40435. After VCC exceeds the threshold of 4.6V, X40435 will turn off its open circuit discharge terminal RESET output for 200 milliseconds (tPOR). When the 3.3V power supply voltage is higher than 2.9V, the V3MON input monitoring circuit of X40435 will turn off its open circuit leakage terminal V3FAIL output. When both of the above conditions are met, the gate of FET (2N7002) is pulled high and turned on, allowing V2FAIL output to control the gate of MOSFET (in this case, Si3443). If you do not want tPOR delay for 5V input, you can use LOWLINE output instead of RESET output.
The V2MON input of X40435 has a voltage divider for a 3.3V power supply. The configuration of the voltage divider resistor ensures that when the 3.3V power supply voltage reaches 3.6V, the V2MON voltage is 1V. However, when the 3.3V power supply voltage is lower than 3.6V, V2FAIL becomes "LOW" high level, and the MOSFET supplying power to the load is turned on.
When the 3.3V power supply voltage reaches 3.6V, the V2FAIL output is set to "HIGH" high level and the output power is turned off. When the 3.3V or 5V power supply voltage is lower than its corresponding threshold, the 2N7002 device is turned off, the Si3443 gate is pulled high, and the load is turned off again.
